Delay locked loop circuit with time delay quantifier and control

ABSTRACT

A delay locked loop circuit has a quantifier for obtaining a measured delay quantity based on a time delay between an external signal and an internal signal. Based on the measured delay quantity, a delay controller controls a correction delay quantity applied to a signal path of the external signal to synchronize the external and internal signals.

FIELD

The present invention relates generally to integrated circuits, and inparticular to delay locked loops.

BACKGROUND

Delay locked loops (DLL) reside in many integrated circuits for delayingan external signal to obtain an internal signal synchronized with theexternal signal. The internal signal usually serves as a referencesignal for the integrated circuits instead of the external signalbecause the internal signal matches internal operating conditions of theintegrated circuits, such as process, voltage, and temperature, betterthan the external signal does.

A typical DLL uses a delay line to delay the external signal. In mostcases, the external and internal signals are initially not synchronized.The DLL performs a synchronization process to synchronize the externaland internal signals. In the process, the DLL compares the external andinternal signals to detect for a time delay between them. After thecomparison, the DLL adjusts the delay of the delay line by a presetamount of delay to correct the time delay. After the adjustment, the DLLcompares the external and internal signals again then adjusts the delaywith the preset amount to correct any subsequent time delay.

The typical DLL usually repeats the comparison and adjustment many timesto gradually reduce the time delay until the external and internalsignals become synchronized. Repeating the comparison and adjustmentmany times to synchronize the external and internal signals wastes timeand power.

SUMMARY OF THE INVENTION

Various embodiments of the invention provide circuits and methods tooperate a DLL more efficiently.

In one aspect, the DLL includes a pulse generator for generating a pulsewith a pulse width corresponding to a time delay between an externalsignal and an internal signal. A quantifier quantifies the pulse widthto obtain a measured delay quantity. A delay unit is capable of applyinga correction delay quantity to a signal path of the external signal. Adelay controller controls the correction delay quantity based on themeasured delay quantity to synchronize the external and internalsignals.

In another aspect, a method of processing signals includes applying aninitial delay quantity to a signal path of an external signal togenerate an internal signal. A pulse is generated. The width of thepulse corresponds to a time delay between the external and internalsignals. The method also obtains a measured delay quantity based on thewidth of the pulse. The method further applies a correction delay to thesignal path of the external signal based on the measured delay quantityto synchronize the external and internal signals.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a delay locked loop circuit according to an embodiment ofthe invention.

FIG. 2 shows an example of a timing diagram for FIG. 1.

FIG. 3 shows an embodiment of a pulse generator of FIG. 1.

FIG. 4 is a timing diagram for the pulse generator of FIG. 3.

FIG. 5 shows an embodiment of a quantifier of FIG. 1.

FIG. 6 is a timing diagram for the quantifier of FIG. 5.

FIG. 7 shows an embodiment of a delay unit and an embodiment of a delaycontroller of FIG. 1.

FIG. 8 shows another embodiment of a delay unit of FIG. 1.

FIG. 9 shows an embodiment of a correction pass gate of FIG. 8.

FIG. 10 shows a memory device according to an embodiment of theinvention.

FIG. 11 shows a system according to an embodiment of the invention.

DESCRIPTION OF EMBODIMENTS

The following description and the drawings illustrate specificembodiments of the invention sufficiently to enable those skilled in theart to practice it. Other embodiments may incorporate structural,logical, electrical, process, and other changes. Examples merely typifypossible variations. Portions and features of some embodiments may beincluded in or substituted for those of others. The scope of theinvention encompasses the full ambit of the claims and all availableequivalents.

FIG. 1 shows a DLL according to an embodiment of the invention. DLL 100includes a delay unit 120 for applying a correction delay quantity to asignal path 101 of an external signal XCLK to generate an internalsignal DLLCLK. Initially, the correction delay quantity is zero. A pulsegenerator 110 generates pulse 111 based on a feedback version of theDLLCLK signal (CLKFB) and a delayed version of the XCLK signal (CLKIN).The width of pulse 111 corresponds to the time delay between the XCLKand DLLCLK signals. A quantifier 114 obtains a measured delay quantitybased on the width of pulse 111. A plurality of quantifying signalsQ1-QN indicates the measured delay quantity. After the measured delayquantity is obtained, a delay controller 116 activates one of the delaycontrol signals CTL1-CTLN to change the correction delay quantity ofdelay unit 120 from the zero to a quantity equal to the measured delayquantity to synchronize the XCLK and DLLCLK signals.

Delay unit 120, an input buffer 122, and an output buffer 124 form aforward path 106. Input buffer 122 receives the XCLK signal and outputsthe CLKIN signal. Output buffer 124 receives an output signal CLKOUTfrom delay unit 120 and outputs the DLLCLK signal.

A delay model 126 is located on a feedback path 108 for delaying theCLKOUT signal to provide the CLKFB signal. Delay model 126 has a timedelay equal to the sum of a time delay of input buffer 122 and a timedelay of output buffer 124. Delay model 126 includes an input buffermodel 123 and output model buffer 125. In some embodiments, input buffermodel 123 is identical to input buffer 122 and output buffer model 125is identical to output buffer 124. Delay model 126 allows a time delaybetween the CLKIN and CLKFB signals to be equal to a time delay betweenwhen the XCLK and DLLCLK signals. Therefore, generating a pulse 111based on a time delay between the CLKIN and CLKFB signals is equivalentto generating a pulse based on a time delay between the XCLK and DLLCLKsignals.

FIG. 2 shows an example of a timing diagram for FIG. 1. Between times T0and T2, the XCLK and DLLCLK signals are not synchronized, and a delay Dindicates a time delay between them. The CLKIN and CLKFB signals alsohave a time delay equal to time delay D. Pulse generator 110 generatespulse 111 with a width W corresponding to the time delay D. At time T1,delay controller 116 activates a delay control signal CTLX based on thewidth of pulse 111. The CTLX signal represents one of the CTL1-CTLNsignals that corresponds to the measured delay quantity that is neededto correct the time delay D. Between times T1 and T2, delay unit 120applies a correction delay quantity indicated by the CTLX signal tocorrect the time delay D. After the correction, the XCLK and the DLLCLKsignal are synchronized at time T2.

FIG. 3 shows an embodiment of pulse generator 110 of FIG. 1. Pulsegenerator 110 generates pulse 111 having a first edge 302 and a secondedge 304. A first edge creator 312 has a first set of flip flop forproducing edge 302 based on the CLKFB signal. A second edge creator 314has a second set of flip flops for producing edge 304 based on the CLKINsignal. An output unit 306 connects to edge creators 312 and 314 tooutput pulse 111 based on a start signal START and a stop signal STOP.Pulse generator 110 has a reset unit 305 for activating an enable signalEN to start a new pulse based on a reset signal RST*.

FIG. 4 is a timing diagram for the pulse generator of FIG. 3. DLindicates the time delay between the rising edge of the CLKFB signal andthe rising edge of the CLKIN signal. Before time T0, the RST* signal isLOW, forcing the EN signal LOW. The START and STOP signals remain LOW orinactivated when the EN signal is LOW. When both of the START and STOPsignals are LOW, pulse 111 remains LOW and has no edges.

At time T1, the RST* signal goes HIGH. The EN signal switches HIGH whenthe CLKFB signal goes LOW at time T1. When the EN signal is HIGH, edgecreator 312 activates the START signal at the rising of the CLKFB signalat time T2, creating first edge 302 of pulse 111. Pulse 111 remains HIGHbetween times T2 and T3, corresponding to a duration between the risingedges of the CLKFB and CLKIN signals. This duration is the time delayDL. The width W of pulse 111 corresponds to DL.

At time T3 , edge creator 314 activates the STOP signal, creating secondedge 304 of pulse 111. After time T3 , both of the START and STOPsignals are HIGH. Pulse 111 remain LOW and has no edges as long as theSTART and STOP signals remain HIGH. Pulse generator 110 generatesanother pulse when the RST* signal goes LOW and then goes back HIGH.

FIG. 5 shows an embodiment of quantifier 114 of FIG. 1. Quantifier 114has a quantifying delay line 502 and a quantifying logic unit 503.Quantifying delay line 502 propagates pulse 111 through a plurality ofmeasuring delay elements 502.1-502.N to get a plurality of delayedpulses 111.1-111.N. Each of the measuring delay elements 502.1-502.N hasa time delay. The number of the measuring delay elements correspondingto the width of pulse 111 equals the duration of the width divided bythe time delay of each measuring delay element. For example, if theduration of the width is six time units and the time delay of eachmeasuring delay element is two time units, then the number of themeasuring delay elements corresponding to the width of the pulse isthree (six divided by two).

Quantifying logic unit 503 has a quantifying logic portion 504 and astoring portion 506. Quantifying logic portion 504 has a plurality ofquantifying logic gates 504.1-504.N for comparing pulse 111 with each ofthe delayed pulses 111.1-111.N to determine a number of the measuringdelay elements corresponding to the width of pulse 111. Quantifyinglogic gates 504.1-504.N sequentially activate the Out1-OutN signalsduring the comparison between pulse 111 and delayed pulses 111.1-111.N.Storing portion 506 includes a plurality of storing devices 506.1-506.Nfor storing the activation of the Out1-OutN signals in forms of thesignal levels of the quantifying signals Q1-QN. Each of the quantifyingsignals Q1-QN corresponds to a different number of measuring delayelements. But only one of the Q1-QN signals indicates a number of themeasuring delay elements that corresponds to the width of pulse 111. Forexample, if the width of the pulse corresponds to three measuring delayelements, quantifier 114 activates the Q1, Q2, and Q3 signals. Q4through QN are not activated. Among the activated Q1, Q2, and Q3signals, Q3 signal indicates the number (three) of the measuring delayelements that corresponds to the width of pulse 111.

In some embodiments, a quantifying signal has a high signal level (HIGH)when it is activated and a low signal level (LOW) when it is notactivated (inactivated). For example, the Q1, Q2, and Q3 signals have ahigh signal level when they are activated. The inactivated Q4 through QNhave LOW signal levels. In this example, storing devices 506.1-506.3store (or hold) the Q1-Q3 signals HIGH and storing devices 506.4-506.Nhold the Q4-QN signals LOW. Storing devices 506.1-506.N reset all of theQ1-QN signals to the same signal level when the RST* signal changes itssignal level. For example, storing devices 506.1-506.N reset all of theQ1-QN signals to LOW when the RST* signal changes to LOW. In embodimentsrepresented by FIG. 5, each of the storing devices 506.1-506.N includesa flip flop.

FIG. 6 is a timing diagram for the quantifier of FIG. 5. Before time T0,pulse has not entered quantifying delay line 502. Therefore, the outputsof all measuring delay elements 502.1-502.N shows no pulses. TheOut1-OutN signals are HIGH; the Q1-QN signals are LOW. At time T0, pulse111 enters quantifying delay line 502 and all gates 504.1-504.N. Pulse111 exits each measuring delay element at various times. For example,pulse 111 exits delay elements 502.1-502.4 as delayed pulses 111.1,111.2, 111.3 and 111.4 at times T1 , T2 , T3 , and T4, respectively. Acertain number of the Out1-OutN signals sequentially switches LOW whenpulse 111 intersects a certain number of the delayed pulses 111.1-111.N.For example, if the width of pulse 111 corresponds to three measuringdelay elements, the Out1, Out2, and Out3 signals sequentially switch LOWwhen pulse 111 intersects the delayed pulses 111.1, 111.2, and 111.3.When one of the Out1-OutN signal switches LOW, a corresponding one ofthe Q1-QN signals is activated HIGH and remains HIGH. In the examplewhere the width corresponds to three measuring delay elements, the Q1,Q2, and Q3 signals are activated HIGH. However, only the Q3 signalindicates the number (three) of measuring delay elements correspondingto the width. In this case, three measuring delay elements is themeasured delay quantity.

FIG. 7 shows an embodiment of delay unit 120 and an embodiment of delaycontroller 116 of FIG. 1. Delay unit 120 includes a correction delayline 701 and a correction selector 703. Correction delay line 701 has aplurality of correction delay elements 702.1-702.N for applying acorrection delay to the CLKIN signal. Since CLKIN signal is on signalpath 101 of the XCLK signal (FIG. 1), applying a correction delay to theCLKIN signal is equivalent to applying a correction delay to signal path101 of the XCLK signal. In FIG. 7, signal path 101 includes a path fromnode 705 to node 707.

In some embodiments, each of the correction delay elements 702.1-702.Nand each of the measuring delay elements (FIG. 5) has equal time delay.Delay unit 702 applies a delay to signal path 101 using a number ofcorrection delay elements that is equal to the number of measuring delayelements obtained by quantifier 114 (FIG. 5) to correct the delaybetween the XCLK and DLLCLK signals.

Correction selector 703 includes an initial delay selector 706.0 and aplurality of correction pass gates 706.1-706.N, each being located inone of a plurality correction paths 707.1-707.N. Each of the correctionpaths 707.0-707.N is one possible path for the CLKIN signal to propagatefrom node 705 to node 707 to become the CLKOUT signal. Each correctionpath has a different number of correction delay elements. For example,correction path 707.0 has no correction delay elements. Correction path707.1 has one correction delay element 702.1. Correction path 707.2 hastwo correction delay elements 702.1 and 702.2. Path 701.N has Ncorrection delay elements, 702.1 through 702.N. Since each correctionpath has a different number of correction delay elements, eachcorrection path applies a different correction delay quantity to signalpath 101.

Delay controller 116 has a control logic unit 709 for controlling thenumber of correction delay elements applied to signal path 101. Controllogic unit 709 includes a plurality of control logic gates 709.1-709.N.The CTL1-CTLN signals at the outputs of gates 706.1-706.N controlscorrection pass gates 706.1-706.N. The combination of the CTL1-CTLNsignals and the RST* signal control initial delay selector 706.0.

When none of the CTL1-CTLN signals is activated, all correction passgates 706.1-706.N turn off, only initial delay selector 706.0 turns onand allows the CLKIN signal to propagate from node 705 to node 707 viapath 707.0. Since correction path 707.0 has no correction delayelements, path 707.0 applies zero delay to signal path 101. When one ofthe CTL1-CTLN signals is activated, initial delay selector 706.0 turnsoff. The CLKIN signal propagates from node 705 to node 707 via one ofthe correction paths 707.1-707.N.

Control logic unit 709 activates one of CTL1-CTLN signals based on themeasured delay quantity to turn on one of the correction pass gates706.1-706.N to select which one of the correction paths 707.1-707.N forthe CLKIN to propagate from node 705 to node 707. The selectedcorrection path has a correction delay quantity equal to the measureddelay quantity. For example, when the measured delay quantity is threemeasuring delay elements, delay control 116 activates the CTL3 signal,turning on correction pass gate 708.3. The CLKIN signal propagates fromnode 705 to node 707 through correction delay elements 702.1, 702.2 and702.3. In this example, three correction delay elements, which is equalto the number of measured delay quantity, are applied to signal path 101to correct the time delay between the XCLK and DLLCLK signal.

Delay unit 120 further includes an initial enable logic 720 forgenerating an enable signal INT* to control initial delay selector706.0. The combination of the combination of the CTL1-CTLN signals andthe RST* signal allow gates 722 and 724 to either activate or deactivatethe INT* signal. When none of the CTL1-CTLN signals is activated,initial enable logic 720 activates the INT* signal to turn on initialdelay selector 706.0, regardless of the RST* signal. When one of theCTL1-CTLN signals and the RST* signal are activated, initial enablelogic 720 deactivates the INT* signal to turn off initial delay selector706.0.

FIG. 8 shows another embodiment of delay unit 120 of FIG. 1. Delay unit120 includes a correction delay line 801 and a correction selector 803.Correction delay line 801 has a plurality of correction delay elements802.1-802.N. Correction selector 803 includes an initial delay selector806.0 and a plurality of correction pass gates 806.1-806.N. FIG. 9 showsan embodiment of each of correction pass gates 806.1-806.N of FIG. 8. InFIG. 9, each of the correction pass gates 806.1-806.N. allows either thesignal at node IN1 or the signal at node IN2 to pass to node OUT basedon one of the CTL1-CTLN signals on node SEL. For example, when the CTL2signal is high, correction pass gates 806.2 allows the CLKIN signal toenter node IN2 and pass to node OUT and to correction delay element802.1. When the CTL2 signal is low, correction pass gates 806.2 allowsthe signal from correction delay element 802.3 to enter to node IN1 andpass to node OUT to correction delay element 802.1.

A plurality of correction paths 808.0-808.N applies a differentcorrection delay quantity to signal path 101. When none of the CTL1-CTLNsignals is activated, initial delay selector 806.0 allows the CLKINsignal to pass from node IN1 to node 707 to become the CLKOUT signal viacorrection path 808.0. Correction path 808.0 has no correction delayelements. Therefore, path 808.0 applies zero delay to signal path 101.When one of the CTL1-CTLN signals is activated, initial delay selector806.0 allows the signal at node IN2 to pass through. The signal at nodeIN2 is the CLKIN signal after it propagates through certain number passgates via one of the correction paths 808.1-808.N. For example, when theCTL2 signal is high, correction pass gates 806.2 allows the CLKIN signalon path 808.2 to enter. The CLKIN signal propagates through correctiondelay elements 802.2 and 802.1. Initial delay selector 806.0 allows theCLKIN from correction delay elements 802.2 to enter and passes to node707 as the CLKOUT signal.

FIG. 10 shows memory device 1000 according to an embodiment of theinvention. Memory device 1000 includes a main memory 1002 having aplurality of memory cells arranged in rows and columns. The memory cellsare grouped into a plurality of memory banks indicated by bank 0 throughbank M. Row decode 1004 and column decode 1006 access the memory cellsin response to address signals A0 through AX (A0-AX) on address lines(or address bus) 1008. A data input path 1014 and a data output path1016 transfer data between banks 0-M and data lines (or data bus) 1010.Data lines 1010 carry data signals DQ0 through DQN. A memory controller1018 controls the modes of operations of memory device 1000 based oncontrol signals on control lines 1020. The control signals include, butare not limited to, a Chip Select signal CS*, a Row Access Strobe signalRAS*, a Column Access Strobe CAS* signal, a Write Enable signal WE*, andan external signal XCLK.

Memory device 1000 further includes a DLL 1015 for receiving the XCLKsignal to generate an internal signal DLLCLK The DLLCLK signal serves asa clock signal to control a transfer of data on data output path 1016.DLL 1015 has a quantifier for obtaining a measured delay quantity basedon a time delay between the XCLK and DLLCLK signals. Based on themeasured delay quantity, DLL 1015 applies a correction delay quantity toa signal path of the XCLK signal to synchronize the XCLK and DLLCLKsignals. DLL 1015 includes embodiments of DLL 100 of FIG. 1.

In some embodiments, memory device 1000 is a dynamic random accessmemory (DRAM) device. In other embodiments, memory device 1000 is astatic random access memory (SRAM), or flash memory. Examples of DRAMdevices include synchronous DRAM commonly referred to as SDRAM(synchronous dynamic random access memory), SDRAM II, SGRAM (synchronousgraphics random access memory), DDR SDRAM (double data rate SDRAM), DDRII SDRAM, and Synchlink or Rambus DRAMs. Those skilled in the artrecognize that memory device 1000 includes other elements, which are notshown for clarity.

FIG. 11 shows a system 1100 according to an embodiment of the invention.System 1100 includes a first integrated circuit (IC) 1102 and a secondIC 1104. IC 1102 and IC 1104 can include processors, controllers, memorydevices, application specific integrated circuits, and other types ofintegrated circuits. In FIG. 11, IC 1102 represents a processor and IC1104 represents a memory device. Processor 1102 and memory device 1104communicate using address signals on lines 1108, data signals on lines1110, and control signals on lines 1120.

Memory device 1104 includes embodiments of memory device 1000 (FIG. 10)including DLL 1015, which corresponds to DLL 100 (FIG. 1).

System 1100 includes computers (e.g., desktops, laptops, hand-helds,servers, Web appliances, routers, etc.), wireless communication devices(e.g., cellular phones, cordless phones, pagers, personal digitalassistants, etc.), computer-related peripherals (e.g., printers,scanners, monitors, etc.), entertainment devices (e.g., televisions,radios, stereos, tape and compact disc players, video cassetterecorders, camcorders, digital cameras, MP3 (Motion Picture ExpertsGroup, Audio Layer 3) players, video games, watches, etc.), and thelike.

Although specific embodiments are described herein, those skilled in theart recognize that other embodiments may be substituted for the specificembodiments shown to achieve the same purpose. This application coversany adaptations or variations of the present invention. Therefore, thepresent invention is limited only by the claims and all availableequivalents.

1. A circuit comprising: a pulse generator for generating a pulsecorresponding to a time delay between an external signal and an internalsignal; a quantifier including a delay line connected to the pulsegenerator for quantifying the pulse to obtain a measured delay quantity;a delay unit for applying a correction delay quantity to a correctionpath of the external signal; and a delay controller connected to thedelay unit and the quantifier, wherein the delay controller includes acontrol logic unit for selecting the correction delay equal to themeasured delay quantity.
 2. The circuit of claim 1 further includes adelay model connected to the delay unit for delaying an output signalfrom the delay unit to provide a feedback signal to the pulse generator.3. The circuit of claim 1, wherein the pulse generator includes aplurality of edge creators for generating a first edge and a second edgeof the pulse based on the time delay between the external signal andinternal signal.
 4. A circuit comprising: a pulse generator forgenerating a pulse corresponding to a time delay between an externalsignal and an internal signal; a quantifier connected to the pulsegenerator for quantifying the pulse to obtain a measured delay quantity;a delay unit for applying a correction delay quantity to a correctionpath of the external signal; and a delay controller connected to thedelay unit and the quantifier for controlling the correction delayquantity based on the measured delay quantity, wherein the pulsegenerator includes a plurality of edge creators for generating a firstedge and a second edge of the pulse based on the time delay between theexternal signal and internal signal, wherein the pulse generator furtherincludes a reset unit for resetting the pulse generator to generateanother pulse based on a reset signal.
 5. A circuit comprising: a pulsegenerator for generating a pulse corresponding to a time delay betweenan external signal and an internal signal; a quantifier connected to thepulse generator for quantifying the pulse to obtain a measured delayquantity; a delay unit for applying a correction delay quantity to acorrection path of the external signal; and a delay controller connectedto the delay unit and the quantifier for controlling the correctiondelay quantity based on the measured delay quantity, wherein thequantifier includes: a quantifying delay line for propagating the pulse;and a quantifying logic unit connected to the quantifying delay line forcomparing a plurality of delay quantities of the quantifying delay linewith a width of the pulse to obtain the measured delay quantity.
 6. Acircuit comprising: a pulse generator for generating a pulsecorresponding to a time delay between an external signal and an internalsignal; a quantifier including a delay line connected to the pulsegenerator for quantifying the pulse to obtain a measured delay quantity;a delay unit for applying a correction delay quantity to a correctionpath of the external signal; and a delay controller connected to thedelay unit and the quantifier for controlling the correction delayquantity based on the measured delay quantity, wherein the delaycontroller includes a control logic unit for selecting the correctiondelay equal to the measured delay quantity.
 7. The circuit of claim 6,wherein the delay unit includes an initial delay selector for setting adelay of the correction path to zero before the pulse is generated.
 8. Acircuit comprising: a forward path for receiving an external signal toproduce an internal signal, the forward path including a delay unit forapplying a correction delay quantity to a path of the external signal; afeedback path for providing a feedback signal based on a delayed versionof the external signal; a pulse generator connected to the forward andfeedback paths for generating a pulse based on the signal relationshipbetween the feedback signal and an input signal derived from theexternal signal; a quantifier connected to the pulse generator, whereinthe quantifier includes: a plurality of measuring delay elements fordelaying the pulse to provide a plurality of delayed pulses; and aplurality of quantifying logic gates connected to the measuring delayelements for comparing the pulse with each of the delayed pulses todetermined a number of the measuring delay elements to obtain themeasured delay quantity; and a delay controller connected to thequantifier for controlling the correction delay quantity of the forwardpath based on the measured delay quantity.
 9. The circuit of claim 8,wherein the pulse generator includes: a first edge creator for producingone edge of the pulse based on an edge of one of the input and feedbacksignals; and a second edge creator for producing another edge of thepulse based on an edge of the other one of the input and feedbacksignals.
 10. The circuit of claim 8, wherein the delay line includes aplurality of different delay quantities, one of the delay quantitiesbeing equal to the correction delay.
 11. The circuit of claim 8, whereinthe forward path includes: an input buffer to receive the externalsignal to generates the input signal; and an output buffer to output theinternal signal.
 12. The circuit of claim 11, wherein the feedback pathinclude a version of the input buffer connected in series with a versionof the output buffer.
 13. The circuit of claim 8, wherein the feedbackpath includes a delay model for delaying an output signal from theforward path to provide the feedback signal to the pulse generator. 14.A circuit comprising: a forward path for receiving an external signal toproduce an internal signal, the forward path including a delay unit forapplying a correction delay quantity to a path of the external signal; afeedback path for providing a feedback signal based on a delayed versionof the external signal; a pulse generator connected to the forward andfeedback paths or generating a pulse based on the signal relationshipbetween the feedback signal and an input signal derived from theexternal signal; a quantifier connected to the pulse generator forquantifying the pulse to obtain a measured delay quantity; and a delaycontroller connected to the quantifier for controlling the correctiondelay quantity of the forward path based on the measured delay quantity,wherein the pulse generator includes a reset unit for resetting thepulse generator to generate another pulse.
 15. A circuit comprising: aforward path for receiving an external signal to produce an internalsignal, the forward path including a delay unit for applying acorrection delay quantity to a path of the external signal; a feedbackpath for providing a feedback signal based on a delayed version of theexternal signal; a pulse generator connected to the forward and feedbackpaths or generating a pulse based on the signal relationship between thefeedback signal and an input signal derived from the external signal; aquantifier connected to the pulse generator for quantifying the pulse toobtain a measured delay quantity; and a delay controller connected tothe quantifier for controlling the correction delay quantity of theforward path based on the measured delay quantity, wherein thequantifier includes: a plurality of measuring delay elements fordelaying the pulse to provide a plurality of delayed pulses; and aplurality of quantifying logic gates connected to the measuring delayelements for comparing the pulse with each of the delayed pulses todetermined a number of the measuring delay elements corresponding to themeasured delay quantity.
 16. The circuit of claim 15, wherein thequantifier further includes a storing portion connected to thequantifying logic gates for storing the number of the measuring delayelements corresponding to the measured delay quantity.
 17. A circuitcomprising: a forward path for receiving an external signal to producean internal signal, the forward path including a delay unit for applyinga correction delay quantity to a path of the external signal; a feedbackpath for providing a feedback signal based on a delayed version of theexternal signal; a pulse generator connected to the forward and feedbackpaths or generating a pulse based on the signal relationship between thefeedback signal and an input signal derived from the external signal; aquantifier including a delay line connected to the pulse generator forquantifying the pulse to obtain a measured delay quantity; and a delaycontroller connected to the quantifier for controlling the correctiondelay quantity of the forward path based on the measured delay quantity,wherein the forward path includes an initial delay selector forselecting an initial correction delay quantity before the pulse isgenerated.
 18. The circuit of claim 17, wherein the delay controllerincludes a delay control logic connected to the initial delay selectorfor setting the initial correction delay quantity to zero.
 19. A circuitcomprising: a forward path for receiving an external signal to producean internal signal; a feedback path for providing a feedback signalbased on a delayed version of the external signal; a pulse generatorconnected to the forward and feedback paths for generating a pulse basedon the signal relationship between the feedback signal and an inputsignal derived from the external signal; a quantifier connected to thepulse generator for quantifying the pulse to obtain a measured delayquantity; and a delay controller connected to the quantifier forcontrolling a correction delay quantity of the forward path based on themeasured delay quantity, wherein the forward path further includes acorrection selector for setting a correction delay after equaled to themeasured delay quantity after the pulse is generated.
 20. The circuit ofclaim 19, wherein the delay controller includes a delay control logicconnected to the correction selector for setting the correction delayquantity equal to the measured delay quantity.
 21. A circuit comprising:a pulse generator for generating a pulse having a pulse widthcorresponding to a time delay between an external signal and an internalsignal; a plurality of measuring delay elements connected to the pulsegenerator for propagating the pulse through the measuring delayelements; a quantifying logic unit connected to the measuring delayelements for determining a number of the measuring delay elementscorresponding to the pulse width; a plurality of correction delayelements located in a signal path of the external signal for applying anumber of correction delay elements to the signal path; and a controllogic unit connected to the quantifying logic unit for adjusting thenumber of correction delay elements based on the number of the measuringdelay elements to synchronize the external and internal signals.
 22. Thecircuit of claim 21, wherein the pulse generator includes a first set offlip flop for generating a first edge of the pulse based on an edge of afirst delayed version of the external signal.
 23. The circuit of claim22, wherein the pulse generator includes a second set of flip flops forgenerating a second edge of the pulse based on an edge of a seconddelayed version of the external signal.
 24. The circuit of claim 21,wherein the quantifying logic unit includes a plurality of quantifyinglogic gates, each connecting to one of the measuring delay elements forcomparing a delay of a number of the measuring delay elements with thepulse width.
 25. The circuit of claim 24, wherein the quantifying logicunit further includes a plurality of storage devices, each connecting toone of the quantifying logic gates for storing a value corresponding toa number of measuring delay elements within the width of the pulse. 26.The circuit of claim 25, wherein the control logic unit includes aplurality of control logic gates connected to the storage devices foractivating a delay control signal to select a correction of path among aplurality of correction of paths of the external signal.
 27. The circuitof claim 26 further includes a plurality of correction pass gates, eachbeing located in one of the correction of paths and being controlled byone the control logic gates.
 28. The circuit of claim 21, wherein atotal number of the of correction delay elements is equal to or greaterthan a total number of the measuring delay elements.
 29. The circuit ofclaim 28, wherein each of the of measuring delay elements and each ofthe correction delay elements have equal time delay.
 30. The circuit ofclaim 21 further includes a delay model connected to the correctiondelay elements for delaying an output signal from the delay unit toprovide a feedback signal to the pulse generator.
 31. An integratedcircuit comprising: a plurality of cells for holding data; a path fortransferring the data between the cells and data lines and a circuit forgenerating an internal signal based on an external signal to control atransfer of the data on the path, the circuit including: a pulsegenerator for generating a pulse corresponding a time delay between theexternal signal and the internal signal; a quantifier including a delayline connected to the pulse generator for quantifying the pulse toobtain a measured delay quantity; a delay unit capable of applying acorrection delay quantity to a correction path of the external signal;and a delay controller connected to the delay unit and the quantifierfor controlling the correction delay quantity based on the measureddelay quantity, wherein the delay controller includes a control logicunit for selecting the correction delay equal to the measured delayquantity.
 32. A system comprising: a processor; and a memory deviceconnected to the processor via bus lines, the memory device including: aplurality of memory cells; a data path for transferring data between thememory cells the bus lines; and a circuit for generating an internalsignal based on an external signal to control a transfer of the data onthe data path, the circuit including: a forward path for receiving theexternal signal produce the internal signal, the forward path includinga delay unit for applying a correction delay quantity to a path of theexternal signal; a feedback path for providing a feedback signal basedon a delayed version of the external signal; a pulse generator connectedto the forward and feedback paths for generating a pulse based on thesignal relationship between the feedback signal and an input signalderived from the external signal; a quantifier including a delay lineconnected to he pulse generator for quantifying the pulse to obtain ameasured delay quantity; and a delay controller connected to thequantifier for controlling the correction delay quantity of the forwardpath based on the measured delay quantity, wherein the delay controllerincludes a control logic unit for selecting the correction delay equalto the measured delay quantity.
 33. A method of processing signals, themethod comprising: generating a pulse corresponding to a time delaybetween an external signal and an internal signal; quantifying the pulseto obtain a measured delay quantity, wherein quantifying includespropagating the pulse through different measuring delay elements toproduce different delay pulses, and comparing each of the differentdelay pulses with the pulse to obtain the measured delay quantity;applying a correction delay quantity to a correction path of theexternal signal; and controlling the correction delay quantity based onthe measured delay quantity.
 34. The method claim 33, wherein generatinga pulse includes generating a first edge and a second edge of the pulsebased on the time delay between the external signal and the internalsignal.
 35. The method of claim 34, wherein generating a pulse occurswhile the correction delay quantity equals zero.
 36. The method of claim33, wherein applying a correction delay quantity includes applying anon-zero correction delay after the pulse is generated.
 37. The methodof claim 33, wherein applying a correction delay quantity includesapplying the correction delay quantity equal to zero before the pulse isgenerated.
 38. The method of claim 33, wherein applying a correctiondelay quantity includes applying a non-zero correction delay after thepulse is generated.
 39. The method of claim 38, wherein controlling thecorrection delay quantity includes selecting a the correction delayquantity equal to the measured delay quantity after the pulse isgenerated.
 40. A method of processing signals, the method comprising:generating an internal signal based on an external signal; producing afeedback signal based on a delayed version of the external signal;generating a pulse based on the signal relationship between the feedbacksignal and an input signal derived from the external signal; quantifyingthe pulse to obtain a measured delay quantity, wherein quantifyingincludes delaying the pulse to provide a plurality of delayed pulses,and comparing the pulse with each of the delayed pulses to determined anumber of measuring delay elements corresponding to the measured delayquantity; and controlling a correction delay quantity of the forwardpath based on the measured delay quantity.
 41. The method of claim 40,wherein generating an internal signal includes applying a correctiondelay quantity to a correction path of the external.
 42. The method ofclaim 41, wherein the initial delay quantity is zero before the pulse isgenerated.
 43. The method of claim 40, wherein the correction delayquantity is greater than zero after the pulse is generated.
 44. Themethod of claim 40, wherein a correction delay quantity includes settingthe correction delay equal to the measured delay quantity.
 45. Themethod of claim 40, wherein generating a pulse include: producing oneedge of the pulse based on an edge of one of the input and feedbacksignals; and producing another edge of the pulse based on an edge of theother one of the input and feedback signals.
 46. The circuit of claim 45further includes generating another pulse when a reset signal isactivated.
 47. The method of claim 40, wherein quantifying the pulsefurther includes storing the number of measuring delay elementscorresponding to the measured delay quantity.
 48. A method of processingsignals, the method comprising: applying an initial delay quantity to acorrection path of an external signal to generate an internal signal;generating a pulse with a pulse width corresponding to a time delaybetween the external and internal signals; propagating the pulse throughdifferent measuring delay elements to produce different delay pulses;comparing each of the different delay pulses with the pulse to obtain ameasured delay quantity based on the pulse width; and applying acorrection delay quantity to the correction path based on the measureddelay quantity to synchronize the external and internal signals.
 49. Themethod of claim 48, wherein the initial delay is zero before the pulseis generated.
 50. The method of claim 48, wherein the correction delayquantity equals the measured delay quantity.